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NOIV1SN025KA
DATA OUTPUT FORMAT
LVDS Output Channels
The image data output occurs through 32 LVDS data
channels, operating at 620 Mbps in 10-bit mode and
496 Mbps in 8-bit mode. A synchronization LVDS channel
and an LVDS output clock signal synchronizes the data.
The 32 data channels are used to output the image data
only. The sync channel transmits information about data sent
over these data channels (includes codes indicating black
pixels, normal pixels, and CRC).
To perform word synchronization on the output data
stream, a predefined training pattern is sent after startup of
the sensor and during idle times (during FOT, ROT, and in
between frames and lines). This data is used to perform word
alignment on the receiving side.
To decrease the data bit rate at the outputs (and reduce the
power consumption), the sensor can operate in 8-bit mode.
In 10-bit mode, the words on data and sync channels have
a 10-bit length. The words are serialized most significant bit
first. The output data rate is 620 Mbps.
In 8-bit mode, the words on data and sync channels have
an 8-bit length. The words are serialized most significant bit
first. The output data rate is 496 Mbps.
This decreases the data bit rate on the LVDS data
channels. Power consumption is reduced by reconfiguring
the internal bias currents. LVDS channels run at 248 MHz
(DDR) in 8-bit mode.
Serial Link Interface Operation
This sensor ’s serial link interface is based on a
mesochronous clocking system. This means that all data and
control links operate at the same frequency, but their phase
may be different due to skew. The host provides an LVDS
clock as input to the sensor. To compensate for possible large
on-chip delays, the sensor retransmits this clock with the
same delay as that seen by the data (32 data channels) and
control path (one sync channel). The receiver end (generally
an FPGA-based system) performs per-interface skew
compensation.
The data on high-speed serial links can drift due to various
reasons such as skew, jitter, PCB trace delays, process,
voltage, and temperature variations. The receiver performs
per-LVDS interface skew compensation using bit and word
alignment techniques.
To support per-interface skew compensation, the sensor
provides a training mode that allows the system to perform
bit and word alignment on all interfaces.
During idle moments (when the sensor is not capturing
images or during frame and line overhead), the image sensor
transmits training patterns. These patterns are configurable
by means of a register upload and should be chosen such that
these can easily be detected by reducing the risk of
mimicking in the regular data stream.
Bit Alignment
Table 26. LVDS OUTPUT CHANNELS
CONFIGURATION
Configuration
adc_mode 8-bit_mode
(pin) (register) Description
0 0 10-bit mode
1 1 8-bit mode
Output Data
Rate Channel
[Mbps]
620
496
Bit alignment procedures position the sampling edge of
the clock at the center of the data eye window by adding
delay to the data path (using delay taps).
Word Alignment
Word alignment procedures ensure that the reconstructed
parallel data bits are in correct order at the output of the
deserializer. Word alignment is done by looking for well
known training patterns.
0
1
1
0
Not supported
Not supported
N/A
N/A
All major FPGA vendors provide bit and word alignment
methods for their FPGAs. Refer to the FPGA vendor ’s
application for more information on the use of these
The 8-bit mode is selected using the adc_mode pin. The
datablock sync channel is configured accordingly
(8-bit_mode configuration). In 8-bit mode, the eight most
significant bits of the ADC data words are transmitted over
the data channels.
Sync channel encoding is similar to the 10-bit mode. The
two least significant bits of the (configured) sync codes are
omitted and the window ID is transmitted after each frame
synchronization word (the two LSBs are to be ignored).
NOTE: The 8-bit mode can only be used to reduce the
data rate at the cost of image data resolution.
Operating the sensor in 8-bit mode at a higher
clock frequency to achieve higher frame rates is
not supported.
functionalities.
When the host succeeds in a lock for bit and word
alignment procedures, the system enables the sensor for
image acquisition. Specific frame alignment patterns are
transmitted for image frame synchronization purposes.
Frame Format
The frame format is explained by example of the readout
of two (overlapping) windows, as shown in Figure 27 (a).
The readout of a frame occurs on a line-by-line basis. In
this representation, the read pointer goes from left to right,
bottom to top.
Figure 27 indicates that, after the FOT is complete, a
number of lines which only include information of ‘ROI 0’
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